The PCI SIG, overseer of the PCI express standard, has finalized version 2 of the base specification. Features for PCI Express 2.0 include better performance at 5GHz PHY, device virtualization, trusted platforms, and different sizes.
Each x1 lane of PCI-E 1.1 offers 250MBps,which puts a x16 link at 4GBps.The PCI-e 2.0 specification will double the per lane speed to 500MBps,boosting a x16 link to 8GBps.
Intel discovered that systems are constrained by jitter and not voltage margins, and hitting the "jitter budget" is a fundamental requirement for version 2.0.
Five GHz devices have to operate at 2.5GT/s or 5.0GT/s. and the transmitter, receiver, reference clock and channel must all be 5GHz capable to get to that kind of performance.
The virtualization feature will allow multiple Operating systems to run simultaneously and share the platform hardware resources, effectively sharing PCI Express devices.
OS improvements can lead to increased IO attacks on systems, so PCIe 2.0 will try and include better trusted computing. There will be a trusted configuration space, and a trusted configuration access mechanism will be included with modifications to the trusted platform module (TPM) to enable that.
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